1. Technical Field
The present disclosure relates to a speaker device of the MEMS (microelectromechanical systems) type, which includes an electronic test circuit. In addition, the present disclosure relates to a corresponding method for testing the speaker device.
2. Description of the Related Art
As is shown, for example, in FIG. 1, a MEMS speaker 1 comprises a plurality of membranes 2, which are arranged so as to form a planar array. For example, the MEMS speaker 1 is formed by 1024 membranes, which are arranged on thirty-two rows and thirty-two columns.
The MEMS speaker 1 further comprises, for each column, a top electrode T and a bottom electrode B, as well as a top-electrode driving circuit 4 and a bottom-electrode driving circuit 6.
The top-electrode driving circuit 4 is electrically arranged between a first supply node, which is set at a first supply voltage VD, and ground. In addition, the top-electrode driving circuit 4 has an input terminal INT and an output terminal, the latter being connected to the top electrode T.
Operatively, the top-electrode driving circuit 4 is designed to impose the voltage on the top electrode T, in such a way that the latter is substantially close to the first supply voltage VD, or else is substantially zero, according to the voltage present on the input terminal INT. In either case, the output terminal of the top-electrode driving circuit 4 is at low impedance, substantially zero.
The bottom-electrode driving circuit 6 is electrically arranged between the first supply node and ground. Moreover, the bottom-electrode driving circuit 6 has an input terminal INB and an output terminal, the latter being connected to the bottom electrode B.
Operatively, the bottom-electrode driving circuit 6 is designed to impose the voltage on the bottom electrode B, in such a way that the latter is substantially close to the first supply voltage VD, or else is substantially zero, according to the voltage present on the input terminal INB. In either case, the output terminal of the bottom-electrode driving circuit 6 is at low impedance, substantially zero.
The MEMS speaker 1 further comprises, for each row, a membrane electrode M, which is connected to all the membranes 2 of the row. In addition, the MEMS speaker 1 comprises, for each row, a membrane-electrode driving circuit 8.
Each membrane-electrode driving circuit 8 is electrically arranged between a second supply node, which is set at a second supply voltage VD2, and the first supply node. The second supply voltage VD2 is higher than the first supply voltage VD; for example, the second supply voltage VD2 is twice the first supply voltage VD. Moreover, the membrane-electrode driving circuit 8 has an input terminal INM and an output terminal, the latter being connected to the membrane electrode M.
Operatively, the membrane-electrode driving circuit 8 is designed to impose the voltage on the membrane electrode M in such a way that the latter is substantially close, alternatively, to the first supply voltage VD or else to the second supply voltage VD2, according to the voltage present on the input terminal NM. In either case, the output terminal of the membrane-electrode driving circuit 8 is at low impedance, substantially zero.
From a mechanical standpoint, the MEMS speaker 1 is formed in a body of semiconductor material, which comprises a substrate 9 (FIG. 2). The top electrodes T and the bottom electrodes B are fixed with respect to the substrate 9.
As shown in FIG. 2, each top electrode T is formed by a plurality of top-electrode subregions SRT, each of which overlies, at a distance, a corresponding membrane 2. The top-electrode subregions SRT of each column are in ohmic contact with one another so as to form precisely the top electrode T. Moreover, each top-electrode subregion SRT is made, for example, of metal and is hollow so as to enable passage of air. The top-electrode subregions SRT are also known as “top plates”.
Each bottom electrode B is formed by a plurality of bottom-electrode subregions SRB, each of which is arranged underneath a corresponding membrane 2, at a distance from the latter. The bottom-electrode subregions SRB of each column are in ohmic contact with one another so as to form precisely the bottom electrode B. Moreover, each bottom-electrode subregion SRB is made, for example, of metal and is hollow so as to enable passage of air. The bottom-electrode subregions SRB are also known as “bottom plates”.
In practice, each top electrode T overlies, at a distance, the membranes 2 of the column corresponding thereto, which in turn overly, at a distance, the bottom electrode B of this column. Moreover, each bottom electrode B overlies the substrate 9.
Each membrane 2 forms, together with the corresponding top electrode T and with the corresponding bottom electrode B, and in particular together with the corresponding top plate SRT and the corresponding bottom plate SRB, an elementary unit 10, which is also known as “pixel 10”. Moreover, each membrane 2 is mobile with respect to the corresponding top plate SRT and to the corresponding bottom plate SRB, and hence is mobile with respect to the bottom electrode B and to the top electrode T of its own column. For this purpose, each membrane 2 is connected to the corresponding membrane electrode M through a first spring 11 and a second spring 13 in such a way that the membrane 2 can move vertically with respect to fixed portions of the membrane electrode M to which it is connected.
In use, the voltages of the bottom and top electrodes B, T and of the membrane electrodes M are set in such a way that the membranes 2 are subject to electrostatic forces that cause movement thereof in the vertical direction, alternatively towards the corresponding top plates SRT, or else towards the corresponding bottom plates SRB.
In particular, the movement of each membrane 2 is such that it approaches alternatively the corresponding top plate SRT or the corresponding bottom plate SRB, without, however, contacting any of them in order to prevent short circuiting.
In order to prevent short circuiting, present in each pixel 10 are one or more top spacer elements 14, also known as “top dimples”, and one or more bottom spacer elements 16, also known as “bottom dimples”. In particular, in the example shown in FIG. 2, each top plate SRT is associated to a corresponding top dimple 14, which is fixed with respect to the top plate SRT and is arranged between the top plate SRT and the corresponding membrane 2. Moreover, each bottom plate SRB is associated to a corresponding bottom dimple 16, which is fixed with respect to this bottom plate SRB and is arranged between the bottom plate SRB and the corresponding membrane 2.
In practice, each membrane 2 is mobile between i) a first position, in which it is in contact with the bottom dimple 16 of the corresponding bottom plate SRB, and is set at a distance from the top dimple 14 of the corresponding top plate SRT, and ii) a second position, in which it is in contact with the top dimple 14 of the corresponding top plate SRT, and is set at a distance from the bottom dimple 16 of the corresponding bottom plate SRB.
In use, each membrane 2 is hence made to oscillate between the aforementioned first and second positions, in such a way that each pixel 10 generates an acoustic wave, which can be perceived by a listener. In practice, each pixel 10 is able to transduce electrical signals into a respective elementary acoustic wave, the ensemble of the elementary acoustic waves generated by the pixels 10 forming the acoustic wave as a whole emitted by the MEMS speaker 1.
Considering, for example, a single pixel 10, the movement of the respective membrane 2 can be obtained by applying to this membrane 2, to the corresponding top plate SRT, and to the corresponding bottom plate SRB, and hence, respectively, to the corresponding membrane electrode M, to the corresponding top electrode T, and to the corresponding bottom electrode B, the voltages shown in FIG. 3.
For greater clarity, in FIG. 3 it is assumed that the first and second supply voltages VD, VD2 are respectively equal to 25 V and 50 V. Moreover, it is assumed that the membrane 2 is initially latched to the bottom plate SRB, i.e., that it is in the aforementioned first position and that the voltages on the corresponding top electrode T, on the corresponding membrane electrode M, and on the corresponding bottom electrode B are such that, in the absence of variations of voltage, the membrane 2 remains in the first position. For example, it is assumed that the voltages on this top electrode T, on this membrane electrode M, and on this bottom electrode B are, respectively, equal to 0 V, 50 V and 0 V. In this way, in the absence of voltage variations, the membrane 2 remains latched to the bottom plate SRB, thanks to the considerable force of electrostatic attraction present between the membrane 2 and the bottom plate SRB, which exceeds the force of electrostatic attraction present between this membrane 2 and the corresponding top plate SRT. This is due to the fact that, even though the voltage present between the membrane 2 and the corresponding bottom plate SRB is equal to the voltage present between the membrane 2 and the corresponding top plate SRT, the membrane 2 is closer to the corresponding bottom plate SRB than to the corresponding top plate SRT.
This being said, while the voltage on the top electrode T is kept at zero, the voltage on the membrane electrode M is reduced to 25 V, and simultaneously the voltage on the bottom electrode B is raised to 25 V. In this way, the voltage present between the membrane 2 and the corresponding bottom plate SRB vanishes, and consequently the force of electrostatic attraction present between them vanishes. The membrane 2 hence tends to move vertically in the direction of the corresponding top plate SRT, on account of the voltage difference present between the membrane 2 and the corresponding top plate SRT. Next, after the membrane 2 has moved away from the corresponding bottom plate SRB by a distance greater than a distance known as “critical distance”, the voltage on the membrane electrode M is raised to 50 V, whereas the voltage on the bottom electrode B is reduced to 0 V; instead, the voltage on the top electrode T is kept at zero. In this way, the membrane 2 is latched to the top plate SRB. It should be noted how by “latching of a membrane to a plate”, whether top or bottom, is generally meant the fact that this plate is effectively the plate that corresponds to the membrane, i.e., overlies the membrane, or else is overlaid by the membrane, with respect to which it is to a first approximation aligned.
Next, in order to latch again the membrane 2 to the bottom plate SRB, the voltage on the membrane electrode M is reduced to 25 V, and simultaneously the voltage on the top electrode T is raised to 25 V. By so doing, the membrane 2 tends to move vertically in the direction of the corresponding bottom plate SRB, on account of the voltage difference present between the membrane 2 and the corresponding bottom plate SRB. Next, after the membrane 2 is at a distance from the bottom electrode B lower than the critical distance, the voltage on the membrane electrode M is raised to 50 V, whereas the voltage on the top electrode T is reduced to 0 V; instead, the voltage on the bottom electrode B is kept at zero.
In this way, the membrane 2 is latched to the bottom plate SRB.
In greater detail, the membranes 2 are actuated by a control unit 15, which is connected at output to the input terminals INT of the top-electrode driving circuits 4, to the input terminals INB of the bottom-electrode driving circuits 6, and to the input terminals INM of the membrane-electrode driving circuits 8.
The control unit 15 receives at input a clock signal CLK and a frame signal LATCH, which has a frequency equal to one thirty-second of the frequency of the clock signal CLK. In this way, the control unit 15 defines a succession of frames, each of which is formed by thirty-two bits.
The control unit 15 moreover receives a first control signal ROW, a second control signal CTOP and a third control signal CBOT, each of which defines, for each frame, thirty-two bits. These first, second, and third control signals ROW, CTOP, and CBOT hence enable indexing, at each frame, of all the pixels 10 of the MEMS speaker 1. In fact, each bit of the first control signal ROW is associated to a corresponding membrane electrode M, while each bit of the second control signal CTOP is associated to a corresponding top electrode T, and each bit of the third control signal CBOT is associated to a corresponding bottom electrode B.
The clock signal CLK, the frame signal LATCH, and the first, second, and third control signals ROW, CTOP and CBOT can be generated, for example, by an external electronic unit (not shown).
As shown in FIG. 4, the control unit 15 processes the clock signal CLK, the frame signal LATCH, and the first, second, and third control signals ROW, CTOP and CBOT so as to generate corresponding voltages on the input terminals INT of the top-electrode driving circuits 4, on the input terminals INB of the bottom-electrode driving circuits 6, and on the input terminals INM of the membrane-electrode driving circuits 8.
For example, FIG. 4 shows three successive frames, with particular reference to an example pixel, which is associated to the second bit (BIT1) of the first control signal ROW and to the third bit (BIT2) of the second and third control signals CTOP, CBOT, i.e., with particular reference to the pixel the membrane of which i) is connected to the membrane electrode M associated to the second bit of the first control signal ROW, ii) is overlaid by the top plate SRT connected to the top electrode T associated to the third bit of the second control signal CTOP, and iii) overlies the bottom plate SRB connected to the bottom electrode B associated to the third bit of the third control signal CBOT. Moreover, FIG. 4 shows the plots of the voltages VROW1, VCTOP2 and VCBOT2, which are respectively the voltages of the membrane electrode M and of the top electrode T and bottom electrode B corresponding to the example pixel. In addition, in FIG. 4 it is assumed that, during the first frame, the membrane of the example pixel is latched to the bottom plate.
This being said, as regards the first frame, the second bit of the first control signal ROW and the third bit of the second control signal CTOP are at low logic values, while the third bit of the second control signal CTOP is at a high logic value. This implies that, during the second frame, the voltage VROW1 is reduced to VD, and the voltage VCTOP2 is kept at zero, while the voltage VCBOT2 is raised to VD.
During the second frame, the second bit of the first control signal ROW is at a high logic value, while the third bits of the second and third control signals CTOP, CBOT are at low logic values. Consequently, during the third frame, the voltage VROW1 is raised again to VD2, and the voltage VCTOP2 is kept at zero, while the voltage VCBOT2 is set at zero. In this way, in the time that elapses between the three frames shown in FIG. 4, the membrane of the example pixel is brought, starting from the condition of latching to the bottom plate, to the condition of latching to the top plate.
Irrespective of the details regarding the modalities of control of the MEMS speaker 1, there is room to improve the manufacture, or in any case integrity, of the MEMS speaker 1. In particular, testing, given any pixel 10, the capacity of the corresponding membrane to latch to the corresponding top plate and/or to the corresponding bottom plate may be beneficial.